1. Field of the Invention
The present invention relates to a processor for executing instructions in units that are unrelated to the units in which instructions are read, and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor.
2. Description of the Prior Art
Processors conventionally read and execute instructions stored in memory according to a program counter. FIG. 1 is a block diagram showing the basic construction of an example processor.
The instruction memory 4301 stores four 8-bit instructions as one instruction packet.
The program counter 4300 indicates the address of an instruction packet in the instruction memory 4301.
The instruction reading unit 4302 reads the instruction packet indicated by the program counter 4300 from the instruction memory 4301.
The instruction executing unit 4303 executes all four instructions included in the read instruction packet in one cycle.
In this way, a conventional processor can read an instruction packet that is indicated by the program counter and can execute four instructions in the instruction packet.
The above processor has to execute all of the instructions in the read instruction packet in one cycle. Accordingly, when one or more instructions in an instruction packet cannot be executed due to problems with computer system resources such as memory or I/O, none of the instructions in the instruction packet can be executed until such problems are resolved. This slows program execution.